New KV cache compaction technique cuts LLM memory 50x without accuracy loss

MIT researchers developed Attention Matching, a KV cache compaction technique that compresses LLM memory by 50x in seconds — ...
EDN

Last-level cache has become a critical SoC design element

LLC, positioned between external memory and internal subsystems, stores frequently accessed data close to compute resources.
Electronic Design

Hardware Compression Works at the Memory Cache Level

How lossless data compression can reduce memory and power requirements. How ZeroPoint’s compression technology differs from the competition. One can never have enough memory, and one way to get more ...
Electronic Design

Server Processors Stack Up to 1.1 GB of 3D Cache

AMD is leveraging one of its latest families of EPYC server CPUs, code-named Genoa X, in-house to run the electronic design automation (EDA) tools it uses for product development. Based on TSMC's 5-nm ...
Forbes

Memory And Design Advances From The AI Infra Summit

Forbes contributors publish independent expert analyses and insights. This article discusses memory and chip and system design talks at the 2025 AI Infra Summit in Santa Clara, CA by Kove, Pliops and ...
PC World

How does CPU memory cache work?

In the eighties, computer processors became faster and faster, while memory access times stagnated and hindered additional performance increases. Something had to be done to speed up memory access and ...
TechSpot

AMD 3D V-Cache CPU memory used to create incredibly fast RAM disk

Why it matters: A RAM drive is traditionally conceived as a block of volatile memory "formatted" to be used as a secondary storage disk drive. RAM disks are extremely fast compared to HDDs or even ...
Nature

Embedded Dynamic Random Access Memory Design

Embedded Dynamic Random Access Memory (eDRAM) design is rapidly evolving to meet the escalating performance and energy efficiency demands of contemporary processors. This technology has emerged as a ...