Using different processors in a system makes sense for power and performance, but it’s making cache coherency much more difficult. Cache coherency is becoming more pervasive—and more problematic—as ...

With silicon clock scaling largely dead thanks to the laws of physics, computer scientists and chip designers have had to search for performance improvements in other areas -- typically by improving ...

System-Level Design sat down to discuss coherency with Mirit Fromovich, principal solutions engineer at Cadence; Drew Wingard, CTO of Sonics; Mike Gianfagna, vice president of marketing at Atrenta, ...

Scaling processing performance beyond the frequency and power envelope of single core systems has led to the emergence of multi-core clusters. Data access management within such processing systems ...

In the first part of this series on the proposed Cache Coherence Interconnect for Accelerators (CCIX) standard, we talked about the issues of cache coherence and the need to share memory across ...

A fundamentally new approach to cache coherence has been released -- the first in more than three decades. Whereas with existing techniques, the directory's memory allotment increases in direct ...

In addition to the cache-coherence protocol discussed here, Sun already used formal verification successfully to verify other protocol-related problems. Architecture-level protocol verification is a ...